1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to using different dopant-types and different dopant densities to fabricate a semiconductor device with high bias tolerance.
2. Description of Related Art
As the size of semiconductor device is reduced, the channel length is accordingly reduced, resulting in a semiconductor device with a faster operational speed. However, even though the shorter channel length raises the operational speed, a channel length that is too short creates other serious problems. These problems are generally called the short channel effect and are described as follows. If the bias applied on the semiconductor device is kept constant but the channel length is shortened, according to a formula of "electric field (E-field)=bias/channel length", where E-field is measured in units of "V/m", the electrons within the channel gain more energy due to the stronger E-field so that the possibility of an electrical breakdown is higher.
Electric breakdown occurring on a high-bias semiconductor device is usually earlier than a low-bias semiconductor device because a potential crowding phenomenon occurring around a drain surface of a field effect transistor (FET) is earlier for the high-bias device. An electric breakdown voltage therefore can not be easily increased. In order to increase the electric breakdown voltage, the dopant density in drift regions of the FET need to be decreased but the decrease of dopant density consequently reduces the driving current and results in a poor device performance. Moreover, a high-bias device needs to consider a latch-up phenomenon between device components. A loose circuit layout may be taken to solve the latch-up but it then deteriorates the integration of the device.
Conventionally, the electric breakdown voltage of a high-bias device can be obtained by forming an additional isolation structure between the source/drain regions and the gate of a FET so as to increase the distance between each other. The additional isolation structure can reduce the horizontal electric field in the channel of the FET. Moreover, a lightly doping region is formed under the additional isolation structure and the source/drain regions so that hot electron effect can be reduced and increase the tolerance of high bias. The high-bias device thereby can normally works at a high bias power source.
FIG. 1 is a cross-sectional view of a conventional high-bias device. In FIG. 1, a field oxide structure 102, an additional isolation structure 103 and a gate 104 are formed on a p-type semiconductor substrate. In the substrate 100, an N.sup.+ -type source region 106 and an N.sup.+ -type drain region 108 are formed around the gate 104. The additional isolation structure 103 is located between the gate 104 and the source/drain region 108. A P-type doped region 110 is formed under the source region 106 and an N.sup.- -type doped region 112 is formed under the additional isolation structure 103. The additional isolation structure 103, the P-type doped region 110, and the N.sup.- -type doped region 112 are used to solve the problems of the short channel length so that the electric breakdown voltage can be increased to allow the device to work at a high bias source.
However, the N.sup.- -type doped region 112 locates beside the N.sup.+ -type drain region 108, which still has a contact area with the substrate 100. The potential crowding phenomenon can still easily occurs at the contact area. The electric breakdown voltage is not as high as the one desired. Moreover, it is insufficient of available space for adjusting the electric field specially used for the high-bias device.